1. Field of the Invention
The present invention relates generally to semiconductor devices, and more specifically, to trench type power semiconductor devices with sidewall spacer gates and a method for fabricating the same.
2. Description of the Prior Art
Trench type power semiconductor devices such as power MOSFETs are well known. For example, referring to FIG. 1 there is shown a portion of a power MOSFET 100 according to the prior art. MOSFET 100 includes a semiconductor body 14 having an epitaxially grown silicon layer 16 (sometimes referred to as an epitaxial layer or as the drain epi region) of one conductivity (e.g. N-type) formed over a silicon substrate 18 of the same conductivity, but of higher concentration of impurities. A channel region 20 (sometimes referred to as the body region) is formed in drain epi region 16 and extends from the top surface of the semiconductor body to a first depth. Channel region 20 has a conductivity opposite to that of drain epi region 16 (e.g. P-type). Formed within channel region 20 are source regions 22, which have the same conductivity (e.g. N-type) as drain epi region 16.
MOSFET 100 also includes a plurality of gate trenches, such as gate trench 12, formed in semiconductor body 14. A gate insulation layer 24 typically lines the sidewalls and bottom surface of the gate trenches. This insulation layer may be formed with silicon dioxide or the like. A conductive gate electrode 26 is disposed within each gate trench 12. Each gate electrode 26 is typically formed as a thick conductive polysilicon gate mass that fills the gate trench.
MOSFET 100 further includes a source electrode 28, which is electrically connected to source regions 22, and may also include high conductivity contact regions 30 formed in channel region 20. High conductivity contact regions 30 are highly doped with dopants of the same conductivity as channel region 20 (e.g. P-type) in order to reduce the contact resistance between source electrode 28 and channel region 20. Power MOSFET 100 further includes a drain electrode 32 in electrical contact with silicon substrate 18.
In power semiconductor devices like MOSFET 100, the gate trenches 12 typically extend at least through the entire thickness of channel region 20, and in particular, often extend into drain epi region 16. Similarly, the gate electrodes 26 typically overlap at least a portion of source regions 22, and extend through channel region 20 and often into drain epi region 16. With this configuration, the gate electrodes 26 fully overlap channel region 20 and allow for the formation of an accumulation region through the channel region so that current will flow between source electrode 28 and drain electrode 32.
In general, the configuration of gate trenches 12 and gate electrodes 26 in power semiconductor devices like MOSFET 100 create several issues. For example, as is known, the overlap of drain epi region 16 and gate electrodes 26 determines the gate-drain charge (Qgd) of the device, which can affect the switching frequency of the device. In general, it is desirable to reduce this overlap and to keep the gate-drain charge as small as possible. Nonetheless, it can be difficult to reduce this overlap/gate-drain charge. For example, one technique used to reduce the overlap is to use thin gate trenches 12, thereby reducing the size of the gate electrodes 26. However, the cleaning of thin gate trenches during device fabrication can be difficult, leading to trench defects.
Another technique used to reduce the gate-drain charge is to increase the thickness of gate insulation layer 24 along the bottom surface of the gate trenches 12. However, while it is desirable to make this region of gate insulation layer 24 thick, it is also desirable to keep the gate insulation layer 24 thin along the sidewalls of the gate trenches so as to keep the device threshold voltage (Vth) low. Unfortunately, the fabrication of a gate insulation layer 24 with varying thicknesses is often a complicated process sequence.
As is also known, it is desirable to keep the size of gate electrodes 26 in power semiconductor devices like MOSFET 100 small to reduce the gate charge (Qg) of the electrodes and thereby improve the efficiency of the device. One technique used to form small gate electrodes is to use thin gate trenches 12, as described above. However, as also described above, the use of thin trenches can lead to trench defects. Another technique used to reduce the size of the gate electrodes is to recess the electrodes into the gate trenches, as shown by MOSFET 100. As an example, gate electrodes 26 of a semiconductor device like MOSFET 100 may be formed by depositing a thick layer of polysilicon that fills trenches 12 and then etching the polysilicon back. As discussed above, it is desirable to have the gate electrodes overlap source regions 22. In general, it can be difficult to control the polysilicon recess depth to obtain this overlap when etching back a thick polysilicon gate mass.
Another problem with thick polysilicon gates 26 is that voids may form in the polysilicon as the polysilicon is deposited into the trenches 12. Such voids can trap charge that cause instabilities in the threshold voltage (Vt) and drain-to-source leakage current (Idss) of the device.
A further problem with gate trenches 12 and gate electrodes 26 is that it is desirable to have the gate trenches and thereby the gate electrodes extend into drain epi region 16 to ensure the gate electrodes overlap channel region 20, as discussed above. However, it can be difficult to control the trench etch depth to obtain sufficient overlap while not over etching the trenches. Again, over etching the trenches results in larger gate electrodes and thereby increased gate-drain charge and increased gate charge.